NPTEL : NOC:Digital Circuits and Systems (Electronics and Communication Engineering)

Co-ordinators : Prof. Shankar Balachandran


Lecture 1 - Introduction

Lecture 2 - Basic Boolean Logic

Lecture 3 - Boolean Theorems

Lecture 4 - Definitions, SoP and Pos

Lecture 5 - Algebraic Minimization Examples

Lecture 6 - Introduction to Verilog

Lecture 7 - Universality, Rearranging Truth Tables

Lecture 8 - Karnaugh Maps

Lecture 9 - K-Map Minimization

Lecture 10 - K-Map with Don't cares

Lecture 11 - Multiple Output Functions

Lecture 12 - Number Systems

Lecture 13 - Encoders and Decoders

Lecture 14 - Multiplexers

Lecture 15 - Multiplexer based Circuit Design

Lecture 16 - Verilog

Lecture 17 - Compiling and Running Verilog - A Demonstration

Lecture 18 - Sequential Elements

Lecture 19 - Gated Latches

Lecture 20 - Flipflops

Lecture 21 - Verilog - Assign Statement and Instantiation

Lecture 22 - Sequential Circuits

Lecture 23 - CMOS+Electrical Properties

Lecture 24 - Delays

Lecture 25 - Sequential Element Delays

Lecture 26 - More Sequential Circuits

Lecture 27 - Introduction to State Machines

Lecture 28 - Always Statement in Verilog

Lecture 29 - Sequential Logic Synthesis

Lecture 30 - FSM Design Problems

Lecture 31 - State Minimization

Lecture 32 - State Assignment

Lecture 33 - Timing Sequential Circuits

Lecture 34 - Verilog Styles + Sequential Elements

Lecture 35 - GCD Algorithm

Lecture 36 - GCD Machines Datapath

Lecture 37 - GCD State Machine

Lecture 38 - GCD Top Level Module

Lecture 39 - Datapath in Verilog

Lecture 40 - Datapath Elements in Verilog

Lecture 41 - FSM in Verilog

Lecture 42 - Putting it all together

Lecture 43 - Pipelining

Lecture 44 - K-stage Pipeline

Lecture 45 - Interleaving and Parallelism

Lecture 46 - Blocking and Non-blocking Statements

Lecture 47 - Modeling Circuits with Pipelining

Lecture 48 - Signed Number Representation

Lecture 49 - Signed Number Addition

Lecture 50 - Adder/Subtracter

Lecture 51 - Fast Adders

Lecture 52 - Multiplication

Lecture 53 - Closing