NPTEL : Advanced Logic Synthesis (Electronics and Communication Engineering)

Co-ordinators : Mr. Dhiraj Taneja


Lecture 1 - MOS Transistor

Lecture 2 - MOS Transistor - Detailed Study

Lecture 3 - Combinational Circuits and layout

Lecture 4 - Delay

Lecture 5 - Sequential Circuits

Lecture 6 - Logical Effort

Lecture 7 - Circuit Families

Lecture 8 - Lab-01

Lecture 9 - Lab-02

Lecture 10 - Lab-03

Lecture 11 - Lab-04

Lecture 12 - Introduction to Synthesis

Lecture 13 - Libraries

Lecture 14 - RTL Coding for Synthesis

Lecture 15 - Reading Design in DC

Lecture 16 - Design Environment

Lecture 17 - Design Constraints

Lecture 18 - Compile Flow and stratergies

Lecture 19 - Analysis and Reporting

Lecture 20 - Lab-05

Lecture 21 - Advanced Synthesis Techniques

Lecture 22 - Datapath Extraction Guidelines

Lecture 23 - Power - Methodology and Analysis

Lecture 24 - Lab-06

Lecture 25 - Lab-07

Lecture 26 - Lab-08

Lecture 27 - Lab-09

Lecture 28 - Static Timing Analysis - Concepts and Flow

Lecture 29 - Interconnects and Delay calculation

Lecture 30 - Clock and Exceptions

Lecture 31 - On Chip Variation

Lecture 32 - Introduction to Crosstalk

Lecture 33 - Gaussian / Normal Distribution

Lecture 34 - Equivalence Checking / Formal Verification